1. Field of the Invention
The present invention generally relates to semiconductor devices and more particularly, to output buffer circuits for such devices and operating method therefor in which output noise is reduced without delaying the output data therefrom.
2. Description of the Prior Art
Recently, semiconductor devices have been significantly developed. In various semiconductor devices, still higher operating speed and more stabilized operation are achieved.
FIG. 1 is a circuit diagram showing an example of a conventional output buffer circuit in a semiconductor device. Such an output buffer circuit is provided in every kind of semiconductor integrated circuit, for example, a dynamic RAM, and generally serves to output an internal signal of such a semiconductor integrated circuit. In a semiconductor device 110 shown in FIG. 1, a conventional output buffer circuit 11 comprises a NAND circuit 14 receiving, as inputs, a signal a supplied from a signal source 10 and a signal b supplied from an output control circuit 12, a NOR circuit 15 receiving, as inputs, the signal a of the signal source 10 and the inverted value of the signal b of the output control circuit 12, an output driving circuit 16 and an output terminal 17.
More specifically, the output driving circuit 16 comprises a p channel MOS transistor Q1 having its source connected to a power-supply voltage V.sub.CC, its drain connected to the output terminal 17 and its gate connected to an output of the NAND circuit 14 and an n channel MOS transistor Q2 having its source connected to a ground potential GND1, its drain connected to the output terminal 17 and its gate connected to an output of the NOR circuit 15. When the semiconductor device 110 is actually used, the output terminal 17 is parasitically connected to large output capacitance or substrate capacitance C comprising interconnection capacitance of the substrate, input capacitance to another device, and the like, as represented by a broken line in FIG. 1. Such substrate capacitance C is also subjected to the effect of radiation. Thus, the p channel MOS transistor Q1 and the n channel MOS transistor Q2 must drive such large output capacitance C at a high speed, so that transconductance of the MOS transistors is set very large. More specifically, the actual size w of the p channel MOS transistor Q1 may be approximately 300 .mu.m while that of the n channel MOS transistor Q2 may be approximately 230 .mu.m.
In addition, there exists a resistance component R.sub.1 and an inductance component L.sub.1 between the ground potential GND1 in the semiconductor device 110 and a ground potential GND2 in a system in which the semiconductor device 110 is incorporated, caused by leads of the semiconductor device itself and external interconnections.
FIG. 2 is a waveform diagram for explaining an operation of the conventional output buffer circuit 11 shown in FIG. 1.
It is assumed that the output signal b of the output control circuit 12 is at an "L" level. In this case, if the output signal a of the signal source 10 is at an "H" level, an output signal c of the NAND circuit 14 attains the "H" level, so that the p channel MOS transistor Q1 is turned off. In addition, an output signal d.sub.2 of the NOR circuit 15 attains the "L" level, so that the n channel MOS transistor Q2 is also turned off. On the other hand, if the output signal a of the signal source 10 is at the "L" level, the output signals c and d.sub.2 attain "H" and "L" levels, respectively, so that both the MOS transistors Q1 and Q2 are turned off. More specifically, if the output signal b of the output control circuit 12 is at the "L" level, the output signal c of the NAND circuit 14 is fixed at the "H" level, irrespective of whether the output signal a of the signal source 10 is at the "H" or "L" level, so that the p channel MOS transistor Q1 is always turned off. In addition, the output signal d.sub.2 of the NOR circuit 15 is fixed at the "L" level, so that the n channel MOS transistor Q2 is always turned off. Thus, when the output signal b of the output control circuit 12 is at the "L" level, an output data signal e.sub.2 is not outputted from the output terminal 17.
Then, it is assumed that the output signal b of the output control circuit 12 is at the "H" level. In this case, if the output signal a of the signal source 10 is at the "H" level, the output signal c of the NAND circuit 14 attains the "L" level, so that the p channel MOS transistor Q1 is turned on. In addition, the output signal d.sub.2 of the NOR circuit 15 is at the "L" level, so that the n channel MOS transistor Q2 is turned off. Thus, in this case, the output data signal e.sub.2 of the "H" level is outputted from the output terminal 17. On the other hand, if the output signal a of the signal source 10 is at the "L" level, the output signal c of the NAND circuit 14 attains the "H" level, so that the p channel MOS transistor Q1 is turned off. In addition, the output signal d.sub.2 of the NOR circuit 15 attains the "H" level, so that the n channel MOS transistor Q2 is turned on. Thus, in such a case, the output data signal e.sub.2 of the "L" level is outputted from the output terminal 17.
FIG. 2 illustrates a waveform for explaining the operation of the output buffer circuit 11 to occur when the output signal b of the output control circuit 12 shown in FIG. 1 is at the "H" level.
It is assumed that the output signal a of the signal source 10 is changed from the "H" level to the the "L" level as shown in FIG. 2(1). In this case, the output signal d.sub.2 of the NOR circuit 15 is changed from the "L" level to the "H" level as shown in FIG. 2(2). The output signal e.sub.2 is responsively changed from the "H" level to the "L" level during the time period t.sub.2 as shown in FIG. 2(3).
Meanwhile, large output capacitance C is parasitically connected to the output terminal 17 as described above. Consequently, when the output data signal e.sub.2 is changed from the "H" level to the "L" level, excessive discharge current i.sub.2 as shown in FIG. 2(4) flows to ground through the n channel MOS transistor Q2. As obvious from FIG. 2(4), when the potential difference between a source and a drain of the n channel MOS transistor Q2 is large, i.e., when the output data signal e.sub.2 starts to be inverted, the discharge current i.sub.2 rapidly flows. However, there exists a resistance component R.sub.1 and an inductance component L.sub.1 between the ground potential GND1 in the semiconductor device 110 and the ground potential GND2 in the system in which such semiconductor device 110 is included as described above, so that the ground potential GND1 in the semiconductor device 110 rises by a voltage V.sub.2 with respect to the ground potential GND2 in the system as shown in FIGS. 2(5) and 2(6), when the discharge current i.sub.2 flows. This voltage V.sub.2 can be expressed as follows: ##EQU1##
As obvious from this equation (1), the larger the discharge current i.sub.2 becomes and the larger the value of di.sub.2 /dt becomes, the higher the ground potential GND1 rises. Since the current is expressed as follows: ##EQU2## the larger the parasitic capacitance C coupled to the output terminal 17 shown in FIG. 1 becomes, the more the discharge current i.sub.2 flows and the larger the rise V.sub.2 of the ground potential GND1 becomes. In addition, the steeper the current i.sub.2 changes, the larger the value of di.sub.2 /dt becomes, so that the rise V.sub.2 of the ground potential GND1 is particularly large when the output data signal e.sub.2 starts to be inverted. As a result, output noise is produced due to such rise V.sub.2 of the ground potential in the conventional output buffer circuit of the semiconductor device 110. More specifically, if it is assumed that the ground potential GND1 in the semiconductor device 110 temporarily rises by the voltage V.sub.2 as described above, an input level to the semiconductor device 110 temporarily falls by V.sub.2 from the true level with respect to the semiconductor device 110. If such fall of the ground potential is in excess of a determination level of an input circuit, this means that false data is inputted to the semiconductor device 110, resulting in malfunction of the whole device.
On the other hand, in the conventional semiconductor circuit for driving a TTL circuit, an RC circuit (not shown) is connected to the gate of the n channel MOS transistor Q.sub.2 at the side of the ground potential in order to obtain a large fan out. As a result, the gate potential of the n channel MOS transistor Q.sub.2 rises gently, so that steep discharge current i.sub.2 can be controlled. However, such slow rising of the gate potential of the n channel MOS transistor Q2 necessarily causes delay of an output data speed, and therefore, such circuit structure is unsuitable for a semiconductor device such as a dynamic RAM in which a high output data speed is required.